Based on an ultra-low-power 30-MHz ARM Cortex-M0+ processor, LPC800 is fully compatible with the Cortex-M architecture and instruction set and offers superior code density to 8- / 16-bit architectures. The Cortex-M0+ features a two-stage pipeline that reduces power consumption while improving performance.
LPC800 MCUs also take advantage of the Cortex-M0+ peripheral bus, allowing single-cycle access to the GPIOs. These features enable NXP LPC800 MCUs to offer deterministic, real-time performance – a key requirement for 8-bit developers.
LPC800 includes game-changing features, such as a switch matrix that enables designers to assign on-chip peripherals to any pin with a single line of code or a single click in the configuration tool.